1. Field of the Invention
The present invention relates to a system controller for controlling a cache device constituting a multi-processor system, and to a cache control method for controlling the cache device. The present invention may be applied to a system controller and a cache control method that are capable of reducing occurrence of retry due to an address conflict between accesses while snooping processes are performed.
2. Description of the Related Art
With increasing need for higher processing speed for computer systems, each CPU in a conventional multi-processor system has been equipped with a cache device. The cache device provided for each CPU manages its data in individual blocks, in accordance with a rule called a cache coherence protocol for maintaining the coherence among cache memories, so as to keep the correctness of the data, i.e. to maintain the shared status and coherence of the data among the cache devices.
MESI cache protocol has been known as a conventional and common cache protocol. The protocol controls four statuses of M, E, S, I. M indicates “Modified” status where, in a plurality of cache devices, only one apparatus has valid data and the data is modified. Whether the value of the data corresponds to that of the main memory is not assured. E indicates the “Exclusive status” where, in the plurality of cache devices, only one apparatus has valid data. S indicates “Shared status” where the plurality of cache devices have the same data. I indicates “Invalid” status where the data in the cache devices are invalid.
When performing cache control using MESI cache protocol described above, a fetch request (where a CPU refers to a data block stored in a cache device in another CPU) requires a write process (hereinafter referred to as “MS write”) of the data block into the main memory unit, resulting in a longer access time.
Therefore, a configuration utilizing five statuses (with another status “Shared Modified” O (indicating “Owner”) being added to the four statuses of the MESI cache protocol) has been adopted to eliminate the need for the MS write with a fetch process.
However, even the protocol utilizing the five statuses requires, when a fetch process for a system is followed by a store process for the data from another system, a status change request to switch the status of another system from O: “Shared Modified” to I: “invalid.” The store process requires longer time because of the status change request, which affects the access performance of the overall apparatus since such store process by a system on the data block acquired with a fetch request is often performed.
Given that, another technique has been disclosed: in a cache device comprising the cache memory and a cache controller, the cache memory stores 1) a part of data from the main memory in units of blocks in a cache line and 2) information indicating the status of the data blocks in the cache line, and the cache controller controls the cache memory by expressing the status of the data blocks using six statuses of, for example, I: “Invalid”, S: “Shared”, E: “Exclusive”, M: “Modified”, O: “SharedModified”, as well as W: “Writable Modified” where data is to be shared in several stages, when a fetch request is issued.
The technique makes it possible to segentalize the status of the data blocks to be controlled in a cache device, so that occurrence of status change requests to other systems can be reduced, resulting in a higher access speed to the cache device.
FIG. 1 illustrates a snooping process in a relatively small multi-processor system (a lower model without an intervening crossbar switch) and FIG. 2 illustrates a snooping process in a relatively large multi-processor system (a higher model with an intervening crossbar switch).
As shown in FIG. 1 and FIG. 2, when a processor unit (CPU0) requests an access to a memory, the access request to the memory is broadcast to all the system controllers (SC0, SC1)that are relevant to the access, in order to maintain the coherence between cache devices. Each of the system controllers (SC0, SC1) then performs, simultaneously, a snooping process to detect a tag corresponding to the address in the cache device in the processor unit that the controller controls, and to check for conflicts on the target data and resource to be used for the data transfer. The result is communicated between the system controllers (SC0, SC1).
FIG. 3 illustrates a snooping process (with a retry) for a fetch request in a lower model.
The operation to be performed for the memory access process is determined finally, by an overall judgment from all of the obtained results. The result of the judgment must be the same for all the system controllers (SC0, SC1) and must be obtained simultaneously. When any conflict or shortage of resource is detected during the snooping process, the access processing is stopped to retry a snooping process.
However, the snooping control as described above had a problem that the communication time varies according to the distances between the plurality of system controllers, requiring performance of snooping processes that are adjusted in accordance with the size of the multi-processor system.